1. Field of the Invention
The present invention relates to a device and method for suppressing the bit line column leakage current in an array of memory cells during erase verification operations.
2. Description of Related Art
Recently, non-volatile semiconductor memory devices, including for instance EEPROMs (Electrically Erasable Programmable Read Only Memories) and EPROMs (Erasable Programmable Read Only Memories) have been widely used in computer, communication and consumer electronic products. Conventional EEPROMs require two transistors per cell, and generally require a relatively large area per cell. These drawbacks result in higher fabrication costs, and make for a larger overall device. EPROMs have the advantage of using one transistor per cell and are therefore relatively cheaper to fabricate and smaller in size. Flash EPROMs provide for convenient electrical erasure of the entire memory array or blocks of the array. Flash EPROMs whose cell area is similar in size to that of traditional EPROMs have become more popular for high density memory applications.
A conventional flash EPROM memory array generally uses a single transistor with stacked polysilicon gates (e.g. a floating gate and control gate) for each cell within the array. The transistor is formed on a p-type well, having n-type source and drain regions provided within the well. The act of programming a flash EPROM cell can take many forms. One popular approach involves injecting the floating gate of selected cells with electrons which thereby places a net negative charge upon the floating gate and increases the turn-on threshold voltage of the memory cell. As a read voltage is applied to the control gates of the programmed cells, the cells will remain non-conductive and not "turn-on." The act of erasing a flash EPROM cell having a negatively charged floating gate involves removing electrons from the floating gate to lower the threshold voltage. With a lower threshold voltage, the cell will turn on to a conductive state when addressed with a read voltage at the control gate.
During the erase operation, over-erasure occurs if too many electrons are removed from the floating gate, thereby leaving a net positive charge. This positive charge biases the memory cells slightly on, so that a small current may conduct through the channel of the memory cell even when it is not addressed. A number of over-erased cells along a given bit line column can cause an accumulation of leakage current sufficient to induce a false reading. In addition, the leakage current can cause an inaccurate erase verification result if there are any over-erased cells co-existing with a "slow bit" on the same bit line column. A "slow bit" is a cell which is difficult erase, or in other words a cell which proves difficult to lower its threshold voltage below a predetermined maximum value.
Referring now to FIG. 1, a prior art circuit diagram 100 is shown which illustrates bias conditions for a conventional erase-verify scheme in which an erroneous erase verification is caused by the over-erased cells. Cell B is representatively designated as a slow bit which is under the necessary limits for erase verification. In this instance, for a read operation, the wordline (Vwl) of cell B is biased at a verify voltage which generally equals the Vcc level for the circuit 100. The wordlines (Vwl) of the other cells on the same bit line column (e.g. cells A, C, and D) are connected to ground (GND). Under these biasing conditions, if cell D is over-erased, a common result will be that its threshold voltage Vt is negative. With such a negative Vt, a leakage current from cell D will contribute to the bit line current and may result in an erase verification "pass" for cell B.
Erase verification pass generally means that all of the cells in a sector, or in the whole chip, pass the erase verification process. A commonly used procedure after erase verification involves taking steps to compensate for (or recover) the threshold voltage of over-erased cells by "soft-programming." Referring now to FIG. 2, an example flowchart is shown of steps used for soft programming. Step 200 starts the process with step 202 including the pre-programming operations. In step 204 an erasing pulse is sent to a sector of cells (or the whole chip). Each cell is then verified in step 206 to see if the cell "passed." If the cell passes (i.e. the answer is "yes"), then soft programming 208 is applied and the procedure ends 210. If the cell fails (i.e. the answer is "no"), then further erasing pulses 204 are applied to achieve erasure of the cells. In general, soft-programming will not be applied unless all of the cells in a sector, or in the whole chip, pass erase verification.
Referring now to FIG. 3, a schematic diagram is shown of the threshold voltage distribution of cells after the erasure operation. This diagram plots the Threshold Voltage on the horizontal axis versus the cell number in an array of cells (having that threshold voltage) on the vertical axis. The resultant plot 300 shows the distribution of threshold voltages for the cells within an array. Most of the cells have threshold voltages which are in the desired region between Vt.sub.-- min and Vt.sub.-- max. However, some of the cells 302 are not in the desired region, and instead are in the over-erased region below Vt.sub.-- min. Among these over-erased cells, certain soft-programming techniques can be applied in order to "recover" the cell so that it has a threshold voltage higher than Vt.sub.-- min. However, certain "slow bits" 304 still exist. Slow bits are cells which have threshold voltages above the erasing decision level 306 (at Vt.sub.-- max). Such slow bits 304 will cause failure during the read operation, including false verifications.
To address problems such as false verifications, prior art solutions have been configured to reserve more decision margin (e.g. room below Vt.sub.-- max) for cell B during the read operation. One conventional method includes lowering the wordline voltage on the selected cell for erase verification. Referring now to FIG. 4, a modified erase-verify circuit configuration 400 is shown in which the wordline voltage 402 applied to the selected cell B is Vcc minus a delta voltage margin amount, i.e. .DELTA.Vmgn. This scheme is not preferred, however, as it is difficult to determine the necessary value of .DELTA.Vmgn (which primarily depends upon the maximum bit line column leakage). Still another issue regarding the reduction of the wordline voltage (or verify voltage) is that the erased threshold voltages of memory cells in a sector (or in the whole chip) will be smaller than they would be if a normal verify voltage is used. The smaller erased threshold voltages may induce more over-erased cells.
As yet another solution, if a configuration can be made to effectively suppress the bit line column leakage caused by the over-erased cells, then more accurate verification results can be achieved. Referring now to FIG. 5, a device configuration 500 is shown which realizes the suppression of bit line column leakage. In the example, the wordline of the selected cell B has a voltage Vcc applied. The non-selected cells A, C, and D (and so forth) have a negative voltage (for example -V, or -Vcc). If all of the over-erased cells on the same bit line column with cell B can be turned off effectively, then the drain current detected by an associated sense amplifier is coming only from cell B. However, implementation of this approach may be complicated since it is necessary to use a negative charge pump for supplying the negative wordline voltage. Examples of prior art using negative wordline voltages include: U.S. Pat. Nos. 5,396,459; 5,416,738; 5,537,362; 5,557,569; 5,574,686; and 5,581,502. Other art includes U.S. Pat. No. 5,547,652 which uses a negative voltage on the non-selected wordline during certain programming operations, and also during erase operations. In yet another approach, U.S. Pat. No. 5,467,310 discloses a configuration where the source of the active cell is connected to a first level, and the sources of the non-active cells are connected to a power supply (or second level) to insure deactivation.
Accordingly, an improved solution is needed to prevent false readings during erase-verify operations, as caused by over-erased cells in an array memory cells. In particular, the solution would be advantageous if applicable to the desirable flash EPROM cells. The improved erase-verify scheme should be easier to implement, yet should insure inactivity of the non-selected cells during read operations. In particular, the scheme should not require unnecessary hardware overhead, or necessitate a negative voltage on the wordlines of the non-selected memory cells.